This invention relates, in general, to semiconductor devices, and more particularly to a method of fabricating a semiconductor device in which the gate leakage current has been substantially reduced.
The ion implantation of dopants into a semiconductor device will damage or destroy the crystal orientation of the substrate by pushing the atoms out of their normal lattice location. To repair the crystal damage and to activate the dopants that are implanted requires a thermal annealing step after the implant step. The thermal annealing recrystallizes the lattice, and part or all of the implanted ions are activated by substitutionally becoming part of the crystal lattice.
Shrinking device dimensions to sub-micron size includes shallower junctions and narrower gate regions which are found to be sensitive to thermal annealing. Better control of impurity diffusions, for a shallower junction, can be obtained through the use of raPid heating devices such as a Varian IA-200 or a Heatpulse 2101. These devices allow a substrate to be heated to 1200.degree. C. in about 10 to 15 seconds.
Polycrystalline silicon, commonly referred to as polysilicon is used both as a gate material on field effect transistor (F.E.T.) devices and as an interconnect material in many integrated circuits. In self-aligned implant process technology, the source, gate, and drain are all implanted in a single step and heat treated (annealed) in a subsequent step.
However, the combination of polysilicon gate, ion implant and thermal anneal created a problem in which current leaks down the edge of the polysilicon gate to either the source or the drain. This gate leakage problem can probably never be reduced to zero but it can be reduced substantially to an acceptable level.